
module test_top(
   input              clk           ,   //system clk ,50Mhz
   input              rst_n         ,   //system resetn
   //RGMII
   input              i_phy_rxc     ,   //rgmii rxclk
   input              i_phy_rx_ctrl ,   //rgmii rx ctrl
   input       [3:0]  i_phy_rxd     ,   //rgmii rxd[3:0]
   output             o_phy_txc     ,   //rgmii txclk
   output             o_phy_tx_ctrl ,   //rgmii tx ctrl
   output      [3:0]  o_phy_txd     ,   //rgmii  txd[3:0]         
   output             o_phy_rstn    ,   //phy rst,active low

   output      [1:0]  o_linkspeed   ,
   output             o_mdc         ,   //MDIO CLK
   inout              mdio              //MDIO DATA 
  
);

   logic                   clk_100m                                  ;
   logic                   locked                                    ;
   logic                   clk_125m                                  ;
   logic                   clk_125m_rst                              ;
   logic [2 : 0]           test_pattern                              ;
   logic                   user_tx_s_axis_tvalid                     ;
   logic [7 : 0]           user_tx_s_axis_tdata                      ;
   logic                   user_tx_s_axis_tready                     ;
   logic                   user_tx_s_axis_tlast                      ;
   logic [67: 0]           user_tx_s_axis_tuser                      ;
   logic                   user_rx_m_axis_tvalid                     ;
   logic [7 : 0]           user_rx_m_axis_tdata                      ;
   logic                   user_rx_m_axis_tlast                      ;
   logic [63: 0]           user_rx_m_axis_tuser                      ;
   logic [7 : 0]           gmii_rxdata                               ;
   logic                   gmii_rxvalid                              ;
   logic [7 : 0]           gmii_txdata                               ;
   logic                   gmii_txvalid                              ; 


   assign clk_125m_rst = ~locked;

   //loop
   


   clk_gen clk_gen_inst (
      .clk_out1                        ( clk_125m                    ),       
      .clk_out2                        ( clk_100m                    ),      
      .reset                           ( ~rst_n                      ),       
      .locked                          ( locked                      ),      
      .clk_in1                         ( clk                         )      
   );

   vio_test_pattern vio_test_pattern_inst (
      .clk        (clk_125m      ),               
      .probe_out0 (test_pattern  )  
   );


   test_pattern #(
      .TEST_DATA_LEN                   ( 16'd1472                        )
   )test_pattern_inst(
      .i_clk                           ( clk_125m                    ),
      .i_rst                           ( clk_125m_rst                ),
      .i_test_pattern                  ( test_pattern                ),
      .m_axis_tvalid                   ( user_tx_s_axis_tvalid       ),
      .m_axis_tdata                    ( user_tx_s_axis_tdata        ),
      .m_axis_tready                   ( user_tx_s_axis_tready       ),
      .m_axis_tlast                    ( user_tx_s_axis_tlast        ),
      .m_axis_tuser                    ( user_tx_s_axis_tuser        ),
      .s_axis_tvalid                   ( user_rx_m_axis_tvalid       ),
      .s_axis_tdata                    ( user_rx_m_axis_tdata        ),
      .s_axis_tlast                    ( user_rx_m_axis_tlast        ),
      .s_axis_tuser                    ( user_rx_m_axis_tuser        )
   );

   /*-----------------------------------------------------------
                     ENTHERNET stack
   ------------------------------------------------------------*/
   ethernet_top #( 
      .SOURCE_PORT                     ( 16'd5001                    ),
      .SOURCE_IP                       ( {8'd192,8'd168,8'd7,8'd11}  ),
      .SOURCE_IP_MASK                  ( {8'd255,8'd255,8'd255,8'd0} ),
      .SOURCE_MAC                      ( 48'h11_22_33_44_55_66       ),
      .MAC_CRC_ON                      ( 1                           )
   )ethernet_top_inst(

      .i_clk                           ( clk_125m                    ),
      .i_rst                           ( clk_125m_rst                ),           
      .i_config_req                    ( 0),
      .i_config_source_port            ( 0),
      .i_config_source_ip              ( 0),
      .i_config_source_ip_mask         ( 0),
      .i_config_source_mac             ( 0),
      .user_tx_s_axis_tvalid           ( user_tx_s_axis_tvalid       ),
      .user_tx_s_axis_tdata            ( user_tx_s_axis_tdata        ),
      .user_tx_s_axis_tready           ( user_tx_s_axis_tready       ),
      .user_tx_s_axis_tlast            ( user_tx_s_axis_tlast        ),
      .user_tx_s_axis_tuser            ( user_tx_s_axis_tuser        ),
      .user_rx_m_axis_tvalid           ( user_rx_m_axis_tvalid       ),
      .user_rx_m_axis_tdata            ( user_rx_m_axis_tdata        ),
      .user_rx_m_axis_tlast            ( user_rx_m_axis_tlast        ),
      .user_rx_m_axis_tuser            ( user_rx_m_axis_tuser        ),
      .i_gmii_rxdata                   ( gmii_rxdata                 ),
      .i_gmii_rxvalid                  ( gmii_rxvalid                ),
      .o_gmii_txdata                   ( gmii_txdata                 ),
      .o_gmii_txvalid                  ( gmii_txvalid                )
   );

   /*-----------------------------------------------------------
                        MDIO CONFIG 
   ------------------------------------------------------------*/

   ethernet_phy_config ethernet_phy_config_inst(
      .i_clk                           ( clk_125m                    ),
      .i_rst                           ( clk_125m_rst                ),
      .o_link                          ( o_linkspeed[0]              ),
      .o_speed                         ( o_linkspeed[1]              ),
      .o_mdc                           ( o_mdc                       ),
      .io_mdio                         ( mdio                        )
   );

   /*-----------------------------------------------------------
                       PHY layer :RGMII to GMII
   ------------------------------------------------------------*/
   rgmii2gmii_top rgmii2gmii_top_inst(
      .i_gmii_clk                      ( clk_125m                    ),  
      .i_gmii_rst                      ( clk_125m_rst                ),
      .o_gmii_rxdata                   ( gmii_rxdata                 ),
      .o_gmii_rxvalid                  ( gmii_rxvalid                ),
      .i_gmii_txdata                   ( gmii_txdata                 ),
      .i_gmii_txvalid                  ( gmii_txvalid                ),
      .i_rgmii_rxd                     ( i_phy_rxd                   ),
      .i_rgmii_rxctl                   ( i_phy_rx_ctrl               ),
      .i_rgmii_rxc                     ( i_phy_rxc                   ),
      .o_rgmii_txd                     ( o_phy_txd                   ),
      .o_rgmii_txctl                   ( o_phy_tx_ctrl               ),
      .o_rgmii_txc                     ( o_phy_txc                   )
   );


endmodule
